1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to register renaming within data processing systems.
2. Description of the Prior Art
It is known to provide out-of-order data processing systems which utilise register renaming techniques to remove or reduce data dependencies between instructions in a manner which permits a higher degree of parallelisation and/or out-of-order instruction issue. Within such systems, as an instruction is decoded it is determined which architectural registers will serve as destination registers for that instruction and which architectural registers will serve as source registers for that instruction. The system is provided with virtual registers that are greater in number than the architectural registers and may be mapped to architectural registers via a rename table. The rename table will indicate which virtual registers are currently available for use as a destination register. Accordingly, a free/available virtual register will be selected and allocated as the destination register for that instruction. The entry in the rename table will then indicate which virtual register corresponds to that architectural register at the current position within the program flow. In a similar manner, decoding of the instruction will determine which architectural source register(s) are required and will examine the rename table to identify the virtual registers which are currently assigned to store the up-to-date content of the architectural source register(s) at the current point within the program flow.
Using this register mapping information within the rename table the instruction issue/scheduling mechanisms can determine when an instruction is appropriate to issue for execution. One approach is to wait until the source registers for that instruction are all available, i.e. had all been written to the virtual registers as indicated within the rename table.
It will be seen that instructions are delayed in their issue until the content of their source registers is available to be read. Thus, it is desirable to increase the available time between the issue of an instruction which will generate the content of a source register for a later instruction and the time at which it is desired to issue that later instruction. If these dependencies can be lengthened in time, then it is more likely that the source register content will be available when it is desired to issue the later consuming instruction and accordingly the consuming instruction will not have to have its issue delayed waiting for generation of its sources.
It is also known to provide program instructions which set program flags. An example of such instructions are the instructions of the Thumb instruction set of the processors produced by ARM Limited of Cambridge, England. Substantially all of the instructions of the Thumb instruction set set one or more of a plurality of flags. These flags indicate processor state conditions arising out of the execution of the instructions, such as the generation of an overflow, the generation of a carry, the occurrence of a zero result etc. In the architecture concerned there are four flags namely N, Z, C and V. These flags are held within a flag register referred to as the CPSR (current program status register). Not all of the flags are updated by every instruction. Accordingly, one source register input to an instruction which does not update all of these flags will be the most recent copy of the CPSR as generated by a preceding instruction. This is required as since the current instruction will only write some of the flag values within the CPSR, the other of the flag values will have to be taken from their previous values as set by the preceding instruction(s). A problem with this approach is that the dependency chain is very short with most instructions requiring as a source the flag register as generated by the preceding instruction. This hinders rapid operation and efficient scheduling.
Similar problems can also arise with other data granules that are dependencies between instructions.